[time-nuts] Re: pulling some crystals

[glenlist]

frequency tweaks of generated signals is easy as you point out . (I have 
DDS carrier generators in the fabric for generating baseband signal 
sources )

But - one cannot use DDS generated clocks for high fidelity ADC/DAC from 
the FPGA outputs because the jitter on those generated clocks due to 
various internal processes is too high. Needs a crystal clock (which si 
how I do it) .

*******but my problem  this is about system sample rate. (requirement 
for pulling the system clocks to ppb)

What about sample rate conversion in hardware ??? Well ! Spur free / low 
distortion sample rate conversion to ppb at 400 MHz needs a fair bit of 
power and heat to do it with precision/ low spurious (and all my 
spurious must be > 120dB down ) .

Best option for that is probably a Farrow interpolation filter, which 
essentially involves, each sample , (re) calculating the interpolated 
point .  But it isnt cheap to do well over a large f/fs ratio,  and if 
done over small spectrum slabs at high sample rate, generates unwanted 
artifacts elsewhere (they look like shark's teeth) .

So, its easier just to get the sample rate clock lined up....


-glen

On 16/12/2023 9:36 am, Hal Murray wrote:
>> the ultimate clock is used as a sample rate clock for ADC, DAC, FPGA . this
>> drives everything.  I can tweak say frequency offset of the system channels
>> that I generate with internal FPGA DDS, but producing a Part PerBillion
>> accurate sample rate conversion running at 393 MHz sample rate would be a
>> whole world of pain,
> Running a fast DDS in a FPGA is pretty easy once you see it.  "Carry save
> adder" is the buzzword.
>
> The problem is how to make a wide adder go fast.  The trick for a DDS is that
> all you need is the carry out of the adder.  So put FFs along in the carry
> chain as needed to meet timing.  That will delay the carry out by a cycle per
> FF but that doesn't matter for a DDS.
>
> Consider a 16 bit adder with one FF half way along the carry chain.  When that FF is a 1, the high bits in the adder and the carry out will be a cycle behind the low bits.  The next cycle they catch up.  The carry out, the DDS signal, has the same pattern.  It's just shifted in time.  If you fed it to a spectrum analyzer you couldn't tell the difference.
>
> A part per billion is only 30 bits.
>
>