[time-nuts] Re: pulling some crystals

[Hal Murray]

> the ultimate clock is used as a sample rate clock for ADC, DAC, FPGA . this
> drives everything.  I can tweak say frequency offset of the system channels
> that I generate with internal FPGA DDS, but producing a Part PerBillion
> accurate sample rate conversion running at 393 MHz sample rate would be a
> whole world of pain, 

Running a fast DDS in a FPGA is pretty easy once you see it.  "Carry save 
adder" is the buzzword.

The problem is how to make a wide adder go fast.  The trick for a DDS is that 
all you need is the carry out of the adder.  So put FFs along in the carry 
chain as needed to meet timing.  That will delay the carry out by a cycle per 
FF but that doesn't matter for a DDS.

Consider a 16 bit adder with one FF half way along the carry chain.  When that FF is a 1, the high bits in the adder and the carry out will be a cycle behind the low bits.  The next cycle they catch up.  The carry out, the DDS signal, has the same pattern.  It's just shifted in time.  If you fed it to a spectrum analyzer you couldn't tell the difference.

A part per billion is only 30 bits.


-- 
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