[time-nuts] Re: Characterizing a 100M TCXO {External}

[alan bain]

What was your lower frequency limit in the integral for the total
phase noise power (assuming the upper limit was that of the last point
given on the datasheet of 1MHz)?

It makes quite a big difference to the total integrated noise power
and hence to the computed RMS jitter and also the maximum error in the
trapezoid rule will occur at the low frequency tail.

Alan
On Fri, 31 Mar 2023 at 02:26, Jim Muehlberg via time-nuts
<time-nuts at lists.febo.com> wrote:
>
> I was curious about the phase noise numbers and I started plugging them
> into spreadsheets and online calculators.  I cannot seem to get matching
> numbers for integrated jitter.  For oscillator 2, the jpg indicates
> about 66fS on the HP5052.  I took this as the reference.  The SI Time
> <https://www.sitime.com/phase-noise-and-jitter-calculator> online tool
> was admittedly close at 59 fS.  The Marki
> <https://rf-tools.com/jitter/>tool gave 88fS.  My spreadsheet, which
> calculates area with the trapezoidal rule is 76 fS.  I calculated
> another way, by finding the segment jitter in dBc, converting to
> radians, squaring, summing, etc and get about 72 fS.
>
> I am not a mathematician, but this seems simple.  Is there some subtlety
> I am overlooking?  Or should we not be concerned about a few fS?!
>
>
> On 2023-03-25 1:10 PM, Gerhard Hoffmann via time-nuts wrote:
> > Am 2023-03-24 22:00, schrieb Christophe Huygens via time-nuts:
> >> I need some help in
> >> characterizing a 100MHz TCXO (Crystek CVHD-950) which we used before
> >> as a reference for a microwave PLL (ham project, see DUBUS 1/21). It
> >> worked
> >> good from a PN perspective but uses multiple steps to get to the
> >> GPS-locked
> >> 100MHz used as the final reference.
> >>
> >> I am trying to see if there is merit in locking the Crystek directly
> >> and therefore
> >> would like to assess its short term time stability. We intend to make
> >> a bunch
> >> of the above and simple is better here.
> >
> > I've made a takeout from my 432 MHz -> 32 MHz transverter published in
> > DUBUS 2 or 3
> > 2022. It is just the ECS 100 MHz xtal oven, PLL to lock it to 10 MHz
> > and further
> > multiplier to 300 or 400 MHz. My GPS delivers 10 MHz. I simply take
> > the interesting
> > LVCMOS harmonic and dump it into a SAW or LC filter. There seem to be
> > no SAWs for 300 MHz.
> >
> > <
> > https://www.digikey.de/de/products/filter/oszillatoren/172?s=N4IgTCBcDaIKYGMDOACRB7BKwFYwQF0BfIA
> >   >
> >
> > The 10->100 MHz PLL is 4046 + 74LVC161 1/10 divider. The 9046 is not
> > available.
> > With a low enough filter corner, PN depends on the XO only.
> > I asked ECS for the phase noise plots of their 100 MHz oven and got
> > them with
> > no NDA attached, so here it is. I think the layout can accommodate the
> > CVHD-950
> > but this has never been tested. The entire takeout has not yet seen
> > solder.
> >
> > 300 MHz is a more lucky choice WRT amplitude than 400. The oven
> > already delivers
> > LVCMOS so there is not much to be lost by further buffering. 300/400
> > MHz happen to
> > be the fastest clock frequencies for the LMX2594 synthesizer in
> > fractional/integer
> > mode.
> >
> >> 2. How do I go about for 100MHz measurements? Is frequency ok - it
> >> probably
> >> will be for the Crystek? Or do I have to divide (MSI? prescaler? what
> >> s today's
> >
> > My LVC161 prescaler created some spurs at frequencies one would never
> > expect.
> > That's why it has it's own small house now.
> > I'm building stereo downconverters for my Timepod @100 MHz and X-band,
> > but
> > day-time work takes precedence and my VNA is ill.
> > A few empty boards, Gerbers or Altium Designer files are available.
> > Outside EU, Gerber files for JLCPCB will be less ado than a leftover
> > board.
> >
> > regards,
> > Gerhard  DK4XP
> >
> >
> >
> > _______________________________________________
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> --
> Jim
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