[time-nuts] New pics of RFTG-m-Rb, and some comparison details

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Sun Dec 31 05:25:58 EST 2006

Hal Murray wrote:
>> If you mean multiply the 15MHz output by 2/3 to generate 10MHz, simply
>>  use asynchronous divide by 3 counter (2 fliplops) to produce a 5MHz 1/
>> 3  duty cycle (or 2/3) output then filter out the 10MHz 2nd harmonic
>> component with a bandpass filter. The 3rd Harmonic (15MHz) will
>> conveniently be very close to a null (only departure from exact 1/3
>> duty  cycle and clock feedthrough from the divider prevent a perfect
>> null). 
> There is another approach that works to multiply by 2: Use the other edge of 
> the clock.
> I think I saw this in an app-note from Xilinx.  The idea is to use an XOR 
> gate and delay to make a pulse on each clock edge.  If you include a FF as 
> part of that delay then you have a reasonable guarantee that the clock pulse 
> will be wide enough to clock a (similar) FF.
> This only works for slow clocks, but 30 MHz is quite slow for modern logic, 
> at least once you get inside the chip.

The method with the lowest additional phase noise is to use a dual 
conjugate regenerative divider with 2 parallel feedback paths.
One feedback path includes a 5MHz bandpass filter and the other a 10MHz 
bandpass filter.
A couple of amplifiers and a low noise mixer together with an adjustable 
phase shifter for each feedback path complete the somewhat complex device.
When mixed with the input 15MHz frequency the 5MHz produces a 10MHz 
output component whilst the 10MHz conjugate frequency mixes with the 
input 15MHz frequency to produce a 5MHz output component. The amplifiers 
are required to produce net gain in the feedback paths.

This technique is practical for other conjugate frequency pairs such as 
f/4 + 3f/4, f/5 + 4f/5, f/6 + 5f/6 etc., with a practical limit 
somewhere around f/9 + 8f/9.
It is complex but has a better performance than any other method. It has 
been used in 160GHz divide by 4 circuits.


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