[time-nuts] Gate propagation delay jitter
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Tue Apr 10 17:32:26 EDT 2007
Hal Murray wrote:
>> I would like to know what are the common methods of introducing
>> delays as low as 10ps between two outputs in an FPGA. I do not
> I'd try to make the delays within the FPGA the same and then tweak the
> external trace lengths. At that level of detail, you will have to pay
> attention to the lengths of the package traces.
> Most of the discussion was jitter rather than delay/offset. I'd expect a lot
> of troubles trying to get low jitter out of a FPGA unless you dedicate the
> whole chip to this particular task. If anything else is going on it will be
> hard to keep the power supply super clean. It might be fun to measure. It
> would be interesting to see how much jitter action on the other side of the
> chip adds.
> One of the wizards on the fpga newsgroup has a war story about clock jitter
> due to outputs near the clock input switching. I forget the details. It may
> have been a single ended clock input.
Yes ground bounce can play havoc with the effective switching thresholds.
One would expect this effect to be much worse with single ended clocks.
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