[time-nuts] Phase jumps of HP3325A synthesizer ???

[Magnus Danielson]

From: "Ulrich Bangert" <df6jb at ulrich-bangert.de>
Subject: [time-nuts] Phase jumps of HP3325A synthesizer ???
Date: Sat, 7 Jul 2007 15:55:05 +0200
Message-ID: <000001c7c09e$7065bd30$03b2fea9 at athlon>

Ulrich,

> Gents,
> 
> perhaps you know that Bruce and I are working on an linear phase
> comparator similar to the K34-5991A from HP (but with some features of
> today) which should enable us to characterize even "better" oscillators
> at an very small price.

This comes as no supprise to me, as Bruce have mentioned it to me. Naturally it
would be nice to build one of those even if I also have other projects I would
like to do in the field (and is doing I might add).

> If however looked at an scale of an few ns it becomes obvious that there
> is an regular sudden jump in phase of abt. 320 ps (always same
> direction) every 60 seconds or so. Bruce and I have tried to remove
> zillions of possible sources for that without any result. As an last
> resort I made an measurment that recorded the phase comparator's output
> as well as an direct time interval measurement between the positive
> slopes of the input clocks and much to my surprise the jump was already
> to be seen there although buried in a bit more noise due to 20 ps tic
> resolution. 

I could investigate it deeper if I only had my Wavecrest and my HP3325B at the
same place. Need to go and fetch the Wavecrest I guess.

> I am almost sure the FTS-1200 can NOT be the source of these jumps
> because it is at the same time the LO of my GPSDO system. If it were to
> produce regular phase jumps (even that small) they would accumulate to
> an value that would result in an noticeable reaction of the closed loop.
> 
> Therefore the qustion: Has anyone of you an theoretical knowledge about
> the HP3325 that would explain this behaviour or has anyone of you made
> similar findings? In the above example the frequency had been set to
> 10.000000005 Mhz, square output, 5V amplitude, 2.5V dc offset which
> gives an 0 to 5 V when terminated into 50 Ohms. Can it be that the
> effect is due to the sqare output? I made some tests whith seeting the
> phase of the output signal which led to no noticable changes so there
> could be an signifant difference of signal phase behavoiur between sine
> and square generstion.

I think the first thing you should do is to make the performance tests on your
HP3325A. You probably want to do the adjustment procedures too. They are easy
enought if you have the service manual, which I do in original hardprint, but
naturally Agilent is nice to help you out:

http://cp.literature.agilent.com/litweb/pdf/03325-90002.pdf

Chapter 4, 5 and 8 should be of particular interest to you.

The core design of the HP3325A is however that you control a VCO sweeping
30 MHz to 50 MHz and mix that down with a 30 MHz fixed frequency VCO (locked to
10 MHz naturally). The variable VCO is programmed to output frequency + 30 MHz.
The control of this is at 100 kHz comparator frequency where the 30 MHz
reference has been divided by 300 and the VCO is divided by N or N + 1.
Since we want the VCO to run not on 100 kHz multiples of frequency, the phase
comparator is being continously offset. A digital process accumulates
synchronously with the 100 kHz and phase accumulates the fractional N
correction and offsets the phase detector using a 5 bit DAC (presumably for 20
values). This is updated every 10 us. This DAC needs to be emptied and this is
done using a synchronous pulse remove event in which the N + 1 division is
used.

At a frequency of 10.000.000,005 Hz we have the frequency register loaded with
030.000.000,005.0000 Hz and thus sets the N = 300 and loads the fractional
phase accumulator with 000 000 050 000 which is accumulated every 10 us. This
means that the phase accumulator increases by 005 000 000 000 every second.

This means that the accumulator will loop every 200 seconds. If this is your
problem, then trimming the ASI will reduce your problem.

Since we only update the DAC from the top 5 bits, i.e. the top digit and the
top half of the second highest digits range. It will go 10 seconds between each
such update. When that occurs the VCO PLL will jump as a result of that phase
step change. The amplitude of the step change will be 10 us / 20 = 500 ns.

Now, all these 500 ns will worked in over time, but the initial chock may be
something like that. However, these events would occur every 10 seconds.

I need to check if it really is a 5-bit BCD value or 5 bit binary number. 

Now, I would have to analyze things even more deeply in order to figure out
what it is actually doing. The magica fractional counter chip is propritary, so
I would have to fool around with a logic analyzer to get conclusive values.

Cheers,
Magnus