[time-nuts] state of the art devide by ten

[Bruce Griffiths]

Said

Yes, but they don't come in a single DIP package.
A switch tail ring counter or Johnson counter like the 74HC4017 divide
by 10 also works well.
However they don't cascade synchronously and aren't available in 74AC or
later lower jitter logic families.
Depending on the output phase noise of the particular Rubidium source a
74HC4017 may have more than adequate performance for the first divide by 10.
However a low jitter buffer is likely to be required to drive the load.

The simplest way using what is to hand is to use 74xx90's together with
some 74XX74 resynchronising flipflops.
However dedicate each 74XX74 to a single frequency output to minimise
intermodulation between outputs.

Bruce

Said Jackson wrote:
> Hi Bruce,
>
> Wouldn't a Gray counter generate a nice stable sequence of switching  
> events for low jitter? Or how about a synchronous shift register set  
> up as a ring with a one going around in circles through the FF's?
>
> Bye, said
>
>  From iPhone
>
> On Mar 29, 2009, at 21:32, Bruce Griffiths  
> <bruce.griffiths at xtra.co.nz> wrote:
>
>   
>> Bill Janssen wrote:
>>     
>>> I want to construct a divide by ten or a divide by 100 frequency
>>> divider. This is to take my 10 MHz. from my
>>> Rubidium to 1 MHz. or 100 KHz.
>>> I could use the spare 74xx90 chips ( which I have) but I would like  
>>> to
>>> make some thing useful for future
>>> uses. What would be a "through the hole" type of IC that would have  
>>> less
>>> jitter than a 74xx90. I CAN do
>>> surface mount if I have to.
>>>
>>> Thanks
>>> Bill K7NOM
>>>
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>>>
>>>       
>> Bill
>>
>> If you want as low a jitter as is possible with a given logic family
>> don't use a ripple carry (between the divide by 5 and divide by 2
>> sections) device like a 74XX90. unless you use an external flipflop to
>> resynchronise the divided output to the 10MHz clock.
>>
>> CMOS logic families like the 74AC can have a cycle to cycle jitter for
>> an inverter clock buffer as low as 1ps. (Even HCMOS inverters can  
>> have a
>> cycle to cycle jitter of around 4ps).
>> However achieving this requires a suitable clock shaper and a low  
>> phase
>> noise source.
>>
>>
>> Bruce
>>
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>>     
>
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