[time-nuts] time interval with 10 ps resolution using cheap FPGA ?

[Tijd Dingen]

Yes this is very much possible! I am doing a spartan-6 implementation of
a frequency counter that uses some of the ideas in that paper. Both the
coarse counter and interpolator are done in the fpga. For the coarse
counter I use a fast free running counter inside the clock domain of
the frequency under test. This then gets resynchronized into the main
clock domain. The advantage is that there are very few flip-flops that
load the input, which means you can get away with NOT using a IBUFG for
every signal you want to measure. Which is good, since I want multi-
channel.

Anyways, your question was if you could do it with a Papilio. Yes you can.
Some time ago I did some test designs to decide between a spartan-3e and
spartan-6. The result was basically that a counter could be built that
uses the idea of a tapped delay line with trigger started ring oscillator
as excitation. It may come as no surprise that the spartan-6 has a clear
performance advantage.

At that point in time there was also talk of a DIY counter on time-nuts.
See for example the "Frequency counter recommendation" thread starting
december 15 2010 and also in this google group:

http://groups.google.com/group/opencounter/

Unfortunately that project did a good job at playing dead so I downgraded
the weight of that in the total decision. Short version is: I decided to
go with spartan-6 since then the counter has better performance, costs
me about the same design effort.

The main reason to go with spartan-3e would have been for a time-nuts
group effort design. But like I said, project dead == very low weight in
the decision.

Should you still have to buy an fpga board and you want to go for a
spartan-3e board, may I recommend the nexys2 from digilent. It's pretty
good (have used it for several projects), and several people on time-nuts
have one too. See here:

http://groups.google.com/group/opencounter/browse_thread/thread/5d2271f48be78398

hope that answers some of the questions...

regards,
Fred



beale <beale at bealecorner.com> wrote:

> I was interested to see this 2009 Fermilab paper which claims a 10 ps (RMS)
> timing resolution in a TDC (time to digital converter) implented in the
> Altera Cyclone II FPGA, which of course has a much slower clock than that.
>  They call their technique a "wave union TDC", involving multiple readouts
> of an internal ring oscillator triggered by the input signal, permitting
> calibration of the relatively coarse and uneven delay elements in the FPGA.
> http://lss.fnal.gov/archive/2009/conf/fermilab-conf-09-275-e.pdf
>
> I have not worked with them yet, but there are some pretty cheap FPGA
> development boards now-, for example, at the $50 price point for a fully
> assembled "Papilio One" board (hosting a Xilinx Spartan 3e) from Gadget
> Factory.  Has anyone tried to make such an extended-resolution TDC using
> this type of FPGA platform? Any opinions on whether it can be done?