[time-nuts] Sine to LVDS

Javier Herrero jherrero at hvsistemas.es
Sat Sep 10 20:20:55 EDT 2011

El 10/09/2011 22:09, Gerhard Hoffmann escribió:
> There is not much you can do with a LVDS signal on the receiving side 
> but feeding it into
> a FPGA or converting it to something else again, introducing further 
> jitter.
>  Some ADCs may be able to live with the small differential voltage, 
> but they probably could
> benefit from the larger PECL levels.
It is not me who has decided to have LVDS inputs at the other side (and 
yes, the clock at the other sides are used for an ADC and also as a 
reference for a PLL - but mostly that is not my problem...). I also will 
use the signal on my side, but driving an FPGA. I think anyway that for 
a long run of cable (probably there will be 10m between my side and the 
other), LVDS is better than PECL.



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