[time-nuts] Generating a solid PPS from 10Mhz source
magnus at rubidium.dyndns.org
Wed Jan 20 15:01:23 EST 2016
On 01/20/2016 03:21 PM, Attila Kinali wrote:
> On Wed, 20 Jan 2016 14:13:11 +0000
> "Poul-Henning Kamp" <phk at phk.freebsd.dk> wrote:
>>> The test results showed a quite more
>>> detailed structure with few delays over 100ps and most being between
>>> 20ps and 80ps. Interestingly, some were close to 0ps, for which
>>> we have no explanation good explanation.
>> Any on-chip PLL's with "spread-spectrum" to fudge EMI tests ?
> Nope, the cyclone4 PLLs do not support spread spectrum.
> Also, the 0ps positions were stable (suggesting some FPGA
> internal feature to be the cause), but they weren't evenly
> spread over the delay chain.
The timing report and estimator is just to make sure that a synchron
design will work. The type of jitter/noise that you see is kind of
typical. It's not that I don't like FPGA, I love it, but I just don't
trust it for precision timing like that.
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