[time-nuts] time-nuts Digest, Vol 178, Issue 20

[Lifespeed]

Hi

Ok basic GPSDO. You need:

1) The GPS PPS, and it's correction data
2) The OCXO
3) Something to drive the tuning voltage input to the OCXO
4) A way to compare the GPS PPS to the OCXO (usually to a PPS off of the
OCXO)
5) Some sort of digital processing to implement the control loop. 

You have 1 and 2. A quiet reference plus a DAC is the common way to do 3.
There are lots of ways to do 4. With modern GPS modules, you would like a
resolution < 100 ps. Just about anything you can program in C or assembler
will work for 5. 

So, can you implement a sigma delta DAC in an FPGA? Sure you can. Will it be
quiet enough all by it's self .. hmmm.. The comparison circuit done all in
the FPGA is also very doable. There are a lot of "synthetic" processors you
can drop into one. There also are FPGA chips with ARM cores built into them.


Bottom line - yes, you *can* do it in an FPGA. That's not to say it would be
the best way to do it.

Bob,

Thanks for the reply,  can you say more about GPS correction data?  Is that
time of arrival of the radio signal sort of correction?

I already have designed items 3; low-noise voltage reference and 16-bit R2R
ladder dual DAC on SPI bus, and opamp circuits to tune the OCXO, but I plan
to implement the loop filter in the powerful FPGA with arm cores (this
design is much more than a GPSDO). With regards to this circuit I do wonder
if I'll need to sum two DAC outputs with one scaled down for increased
resolution.  A concern might be digital PLL/filter "hunting" trying to make
the minute adjustments needed for phase lock if the DAC circuit cannot make
small steps.

My questions regard true phase/frequency comparison (4) where the OCXO phase
will be truly phase-locked to the 1 PPS.  Even though the digital PLL loop
BW possible (or desired given the low close-in phase noise of the 10MHz
OCXO) is probably less than 0.1Hz, the Allan deviation of 3 X 10^-13 means
the OCXO won't wander around under the control of even a 0.1Hz loop with the
DAC updating every 1 second.  10MHz * 3 X 10^-13 Allan dev yields 3X 10^-6
Hz drift.  It would seem to me the digital PLL/integrator/DAC system would
need to only be able to suppress a 3 microHertz error with miniscule loop
gain and BW.

So is that what a GPSDO typically does, provide a phase-locked output such
that two modules of the same design will have outputs that do not vary their
relative phase relationship?  Or are they just the same frequency within
some small error, but the frequency error is the derivative of a phase error
that has the two signals slowing drifting past each other in phase?

Subject 5, the digital PLL is also interesting, although I understand this
has done before and is just a matter of designing the correct implementation
in FPGA DSP processing fed by a flip-flop phase detector and 10 X 10^6
divider.  I would be glad to hear about any good books or white papers on
the subject.

Lifespeed