[time-nuts] A simple sampling DMTD

[Attila Kinali]

On Sun, 3 Nov 2019 01:41:08 +0100
Jan-Derk Bakker <jdbakker at gmail.com> wrote:

> The test was run for 175k seconds (just over 2 days) in a very much
> non-temperature controlled attic. The resulting ADEV can be found at
> http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20ADEV.pdf ; the

This looks good, but I would still expect the start of the ADEV plot,
ie the precision of the single measurements to be about half an order
to an order of magnitude lower. For comparison, commercial DMTD systems
operate at about 1e-13 at 1s, which is mostly dominated by the mixer
noise and temperature coefficient. I would expect you to be close to
1e-12 at 0.1s, even before filtering.

BTW: For this kind of measurement, TDEV is the more useful measure.

> measured time difference between the channels is
> http://www.lartmaker.nl/time-nuts/DMTD%20self-noise.png ; the input
> spectrum of channel 1 with and without the filters is
> http://www.lartmaker.nl/time-nuts/DMTD%20self-noise%20input%20spectrum.pdf
> 
> For tau=1s the Allan deviation without any filtering is 9.5E-13. High pass
> filtering to eliminate LF noise and drift improves this to 4.6E-13; adding
> bandpass filtering yields 3.2E-13. Out to 1000s the adev decreases linearly
> with tau, after that performance degrades (further testing in a temperature
> controlled room should show whether this is intrinsic or not).

You care mostly about temperature gradients. If both paths are about the
same temperature, then they will get approximately the same change in delay.
Ie put a cardboard box over it and you will have a pretty stable system.

BTW: a rule of thumb for temp coefficients for quite a large group of
components (mixers, DDS, etc) is 1-5ps/°C,

> 
> As the high pass filtering seems to have the largest impact, I plan to
> implement this first (still based on averaging over a single period
> centered around the rising flank of the sine; the on-board processor
> doesn't have enough horsepower to run a 1001pt FIR at 2ksps). Next I want
> to add code to phase lock the on-board VCTCXO to the reference input, this
> should also make it easy to implement a notch filter to eliminate (even)
> harmonics.

You do want the notch filters in front of the ADCs. Once the harmonics
enter the system, they already contributed to noise conversion. Digital
filtering helps only if you can completely separate the harmonics from
the signal, which is not possible due to non-linearity of the ADC.
So, I would suggest to have at least some filtering in the frontend
and then clean up the rest in the digital domain.


> After that I want to see if I can get a computationally
> efficient arcsin/arctan applied to the data, to make it easier to extend
> the number of samples used by the ZCD without running into linearity
> issues. Meanwhile I'm working on a daughterboard with twin Lattice iCE40
> FPGAs.

I don't remember what uC you are using, but CORDIC would be the way to
go in most places, especially if you want lots of bits. You need something
in the order of 2-5 stages more than you want output bits and about as
many intermediate bits more.

			Attila Kinali

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