[time-nuts] Digital Phase Lock Loops

[Jim Harman]

Martyn,

Are you willing/able to write or modify some code to implement the loop?
GPSDOs typically use a digital PLL which can have a time constant of 10,000
sec or more. The biggest challenge with very long time constants is
avoiding overflow and roundoff issues in the calculations.

You might want to study Lars Walenius' GPSDO design as described here
https://www.eevblog.com/forum/projects/lars-diy-gpsdo-with-arduino-and-1ns-resolution-tic/


Unfortunately Lars has passed away but I have modified and extended his
system and can provide some help if you are interested.

On Tue, Nov 19, 2019 at 6:38 AM <martyn at ptsyst.com> wrote:

>
>
> Hello,
>
>
>
> Have anyone had any luck designing a phase lock loop with very small
> bandwidths, e.g. less than 0.2 Hz.
>
>
>
> I need to lock a 100 MHz Ultra low oscillator to a 10 MHz ultra low
> oscillator and I need a loop bandwidth less than 0.2 Hz.
>
>
>
> Quartzlock do a digital PLL board with bandwidths to 1 mHz.  However I
> never
> got it to work.
>
>
>
> The 10 MHz reference has phase noise of -116 dBc/Hz at 1Hz offset.  The 100
> MHz VCO make -104 at 1 Hz.
>
>
>
> Obviously I'm trying to preserve the 100 MHz phase noise.
>
>
>
> Any advice would be appreciated.
>
>
>
> Best Regards
>
> Martyn
>
>
--Jim Harman