[time-nuts] OCXO and fluctuations after EFC adjustment

[Bob kb8tq]

Hi

Well….. 

Once upon a time, there was a design review on a space part. There
was an tantalum  cap used in a couple of places in the design. It was 
a 50V part and running at 12V. 

We got dinged for it. Turns out if you over derate electrolytics (of any sort)
there is a failure mechanism that creeps in. 

How was that discovered? Well NASA (or the military or ….)  sponsored 
severals studies at several universities. They did a bunch of testing and 
published a number of papers on the topic. Quick summary: "tested
a whole bunch and these failed". 

A good librarian with a week or two on their hands probably can track 
them down. I very much doubt you can find them outside a pay wall. 

Bob

> On Apr 12, 2020, at 5:52 AM, Gerhard Hoffmann <ghf at hoffmann-hochfrequenz.de> wrote:
> 
> 
> Am 12.04.20 um 05:22 schrieb Ben Bradley:
>> More recently, I saw this Kemet presentation on Digikey about tantalum
>> capacitors. Certainly for aluminum electrolytic capacitors, the rated
>> voltage is "the rated voltage" and as long as the capacitor never goes
>> ABOVE that voltage (and has no overcurrent that would heat it up,
>> etc.), the cap is good for its combination of temperature and lifetime
>> rating. I (and as far as I know, everone I've known) assumed this was
>> the same for tantalums, but it appears that's not the case (this
>> presentation mentions several failure causes and shows how they are
>> multiplicative). As you go from 1/2 rated voltage to full rated
>> voltage, the chances of a tantalum failing goes up substantially. The
>> implied rule seems to be for maximum reliability, don't operate a
>> tantalum above HALF the rated voltage. I'd heard a lot of anecdotal
>> things about tantalums suddenly shorting out for this or that reason,
>> but hadn't heard of this, and here it is straight from the
>> manufacturer.
>> https://www.digikey.com/en/ptm/k/kemet/derating-guidelines-for-surface-mount-tantalum-capacitors/tutorial
> For a space project, I was surprised that ESA required derating
> of tantalum working voltage only to 50%, where I was used to
> derate down to 1/3 as was proposed in a NEC data sheet from
> 30 years ago. But then, the only allowed Ta caps had 6 times
> the volume of commercial ones, so the first round of derating
> probably was already built-in.
> 
> 
> Those fat capacitors did really hurt, esp. when the proposed
> SEU mitigation of the regulators consisted of providing large
> enough load capacitance so that the regulators could go
> Berserk for a millisecond or two without blowing up the FPGA.
> 
> 
> cheers, Gerhard
> 
> 
> 
> 
> 
> 
> 
> 
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