[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Magnus Danielson]

Hi,

On 2020-01-19 01:28, Mark Haun wrote:
> Hi time nuts,
>
> I'm looking for a 5x frequency multiplication scheme to let me use a
> 16-MHz square-wave OCXO for an ADC encode clock at 80 MHz.
>
> Constraints in order of importance:
>
> 1. Don't degrade the nice phase noise of the OCXO (-90 @ 1, -120 @10,
> -140 @ 100, -160 @ 1k) any more than necessary; at the very least, it
> should not impact the ADC noise floor in the primary 0-40 MHz image. 
> (This should give quite a bit of leeway, but better is better :)
>
> 2. OCXO power consumption (~150 mW) should still dominate total
> clock-system power.  Would like to keep the multiplier/buffer under 50 mW.
>
> 3. No supply rail above 3.3V.
>
> This "ought to be" (?) easy, because the OCXO output is already rich in
> odd harmonics.  All that's needed is to isolate and perhaps buffer the
> right one without screwing up my noise spec.  This is where I could use
> some help...
>
> The ADC (AD9266) wants a differential clock, sinusoidal or square
> doesn't matter.  The datasheet recommends transformer coupling with
> antiparallel diodes to keep the swing ~ 1.5Vp-p.  (The min/max spec says
> anything between 0.2 and 3.6V.)   The 3.3V OCXO should give me 0.8Vp-p
> at the 5th harmonic without any amplification, so in theory I guess I
> could just filter and transformer couple and be on my way.  But perhaps
> some amplification is in order to increase the slew rate?
You should be able to do exactly that.
> I looked at the Wenzel tech notes for ideas, e.g. this one using logic
> gates and tuned circuits:
> http://www.techlib.com/files/hcmos.pdf
> but I lack the background to evaluate the pros and cons of introducing
> extra CMOS logic.
>
> I also found this common-base amp circuit in the archives:
> https://www.febo.com/pipermail/time-nuts/2016-January/095683.html  and
> https://www.febo.com/pipermail/time-nuts/attachments/20160126/ae3b4be8/attachment-0001.pdf
>
> I've read that I should avoid high-Q tuned circuits, because they will
> introduce more noise with temperature variation.  Are there any rules of
> thumb for how much Q is too much?

You do not need very high Q, as suitable LCR will fit. Besides, if there
is any of the other overtones creating issues, you can build LCR links
tuned to these that will consume that energy.

The other fairly obvious solution is as already suggested by Bert is to
use a SiLabs chip. You can get a test-board and test this easy, in fact,
several boards exists which is ridicolously cheap. There is one from QRP
labs which has additional filtering on power to have less noise issues.
It lies there on my lab-bench assembled, but I have yet to measure it.

Regardless if which solution you try, what capability do you have to
test it? It remains an important tool here. There is no golden design
that just solves everything. I've recently measured how very well
performing devices performance was partly lost due to bad design. I use
the old and trusty TimePod.

Cheers,
Magnus