[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Alex Pummer]

the only problem with that CMOS  freq. multiplying circuit's that the 
threshold of the inputs  has a thermal noise component = jitter [phase 
noise]
73
KJ6UHN
Alex

On 1/19/2020 11:31 AM, Mark Haun wrote:
> Hi Jim,
>
> On Sun, 19 Jan 2020 10:35:42 -0800
> jimlux <jimlux at earthlink.net> wrote:
>> On 1/19/20 9:29 AM, Mark Haun wrote:
>>> On Sun, 19 Jan 2020 09:37:39 -0500
>>> Bob kb8tq <kb8tq at n1k.org> wrote:
>>>> Is your intended application tolerant of spurs at 16 and 32 MHz? If
>>>> not, do they need to be in the 90 dB down vicinity (= the SFDR of
>>>> the ADC) ?
>>> I guess you mean stray coupling between the oscillator, clock
>>> conditioning circuitry and the analog inputs?  (Spurs on the ADC
>>> clock input shouldn't matter as long as the zero crossings are
>>> clean and jitter is low.)
>> Not exactly.  The sampler of the ADC is essentially a mixer, so if
>> the clock has other signals on it, even at low levels, they can mix
>> with input signals and show up in band.  I had a SDR receiver with a
>> 49.244 MHz ADC clock that was contaminated by the 66MHz processor
>> clock (at a very, very low level), and I saw mixing products when the
>> input to the ADC was a clean sine wave at 112.5 MHz.
>>
>> Analog Devices even has an app note on this.
>>
>> https://e2echina.ti.com/cfs-file/__key/telligent-evolution-components-attachments/13-109-00-00-00-00-93-58/Impact-of-sampling_2D00_clock-spurs-on-ADC-performance.pdf
> Hmmm, so in my case, other residual odd-order harmonics of the 16 MHz
> input clock which make it through the multiplier will become
> non-harmonic spurs of the desired 80 MHz, and therefore a potential
> problem unless filtered out.  The analog amplifier scheme will
> therefore require decent bandpass filtering, mainly against 16, 48, and
> 112 MHz.
>
> One advantage of the Wenzel CMOS-based multiplier is that the threshold
> behavior of the last inverter [mostly?] gets rid of everything but the
> selected harmonic.
>
> I'm still trying to understand the phase-noise pros/cons of that design
> using, say, a pair of NC7SZ04 (UHS family) gates, versus a discrete
> transistor amplifier tuned at 80 MHz, like the common-base design
> quoted in the original post.
>
> Regards,
> Mark
>
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