[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Attila Kinali]

On Sat, 18 Jan 2020 16:28:56 -0800
Mark Haun <mark at hau.nz> wrote:

> Constraints in order of importance:
> 
> 1. Don't degrade the nice phase noise of the OCXO (-90 @ 1, -120 @10,
> -140 @ 100, -160 @ 1k) any more than necessary; at the very least, it
> should not impact the ADC noise floor in the primary 0-40 MHz image. 
> (This should give quite a bit of leeway, but better is better :)
> 
> 2. OCXO power consumption (~150 mW) should still dominate total
> clock-system power.  Would like to keep the multiplier/buffer under 50 mW.
> 
> 3. No supply rail above 3.3V.
> 
> This "ought to be" (?) easy, because the OCXO output is already rich in
> odd harmonics.  All that's needed is to isolate and perhaps buffer the
> right one without screwing up my noise spec.  This is where I could use
> some help...

With those constraints, and reading the discussion, I wonder why don't
consider a VCXO+PLL solution. Using something like the Abracon ABLNO and
a generic PLL (e.g. ADF4001) would give you above performance. The ABLNO
are so low noise enough, that you can use a low BW loop filter (order of 500Hz)
and get lower output noise than the up-multiplied 16MHz signal above that
and the (multiplied) OCXO performance below that (with a slight bump due
to the PLL around the loop filter frequency).

The big advantage over the multiplier solution is that you don't have to
deal with a high level of harmonics and get a very clean signal with
almost no effort.

			Attila Kinali

-- 
Science is made up of so many things that appear obvious 
after they are explained. -- Pardot Kynes