[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Attila Kinali]

On Mon, 20 Jan 2020 11:13:46 +0100
Attila Kinali <attila at kinali.ch> wrote:

> With those constraints, and reading the discussion, I wonder why don't
> consider a VCXO+PLL solution. Using something like the Abracon ABLNO and
> a generic PLL (e.g. ADF4001) would give you above performance. The ABLNO
> are so low noise enough, that you can use a low BW loop filter (order of 500Hz)
> and get lower output noise than the up-multiplied 16MHz signal above that
> and the (multiplied) OCXO performance below that (with a slight bump due
> to the PLL around the loop filter frequency).

Addendum: I don't know your application, but in a general high-speed
sampling systems, it's the white noise floor that you are worried
about, not the 1/f^a noise. And in that case, having a lown noise XO
produce your sampling clock is better than multiplying a low frequency
OCXO and using this directly, even if the XO is free running.

			Attila Kinali

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