[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

On Mon, 20 Jan 2020 14:22:41 -0500
Bob kb8tq <kb8tq at n1k.org> wrote:
> On Jan 20, 2020, at 1:36 PM, Mark Haun <mark at hau.nz> wrote:
> > The VFOV405 datasheet lists typical phase noise for 10- and 100-MHz
> > units.  (Mine are 16.384 MHz.)  In comparing the two oscillators, I
> > have used the 100-MHz "typical" numbers which they both state:
> 
> So taking the 14 db from multiplication into account:
> 
> 
> 		VFO405		ABLNO		
> 
> 1K 		-126			-141
> 10K		-146			-160
> 100K	-149			-161
> 
> Looking at the plots on the ABLNO data sheets, the wide band noise
> gets down a bit below -161 on a “typical” basis. 
> 
> Locking an 80 MHz ABLNO to 16.384 is not going to be as easy as
> locking one to 16.000. Getting an ABLNO with an EFC at 16.384 x 5 may
> be a bit of a challenge.

Agree except you were starting from the VFOV numbers for the 100-MHz
version.  If you use their numbers for the 10-MHz version and add 20 dB
for an ideal 10x multiplication, for comparing with the ABLNO spec at
100 MHz, you end up with

offset    VFOV405 @ 10M, ideal 10x multiply     ABLNO @ 100 M
10        -100                                  -88
100       -120                                  -118
1k        -140                                  -141
10k       -145                                  -160
100k      -145                                  -161

so not bad apart from the raised floor.  (I am assuming that an ideal 5x
multiplication on the 16.384-MHz version of the VFOV405 would yield a
similar comparison to an 80-MHz ABLNO.)

Using this handy tool: https://rf-tools.com/jitter/  it looks like 0.5
ps should be achievable as long as the floor is kept to -145 dBc/Hz
(integrating 10 Hz to 10 MHz).  The multiplier scheme will need to
contribute very little residual noise far out.  No idea how easy/hard
that will be. More than 0.5 ps jitter will start to degrade the ADC
performance significantly.

Regards,
Mark