[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Attila Kinali]

On Tue, 21 Jan 2020 01:15:45 +0100
Attila Kinali <attila at kinali.ch> wrote:

> > I was about to say that adding a second ADC channel is really expensive
> > (like $50 between AD9266 and AD9269), but I really like this idea...
> > just couple a reference oscillator into the main signal path at an
> > appropriate level, then use a parallel receive path in the FPGA
> > to trim the NCOs for the known beacon frequency.
> 
> You don't need a high performance ADC for the reference as you are dealing
> with a narrow band signal of known frequency. Even a 10bit or 8bit ADC
> would be good enough. You can even go and sample at half frequency
> and save both money and power. 

I just spend a few minutes looking at ADCs and found the LTC2256-12
and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
Both have 170fs RMS apperture jitter and do 25Msps and 40Msps respectively.
3dB BW is 800MHz, so more then good enough to even use the 100MHz output
of an hydrogen maser, if you want a really good reference ;-)

Power consumption at max sample rate are 34mW and 47mW respectively.
That's slightly more than a PLL would use (~20mW, plus maybe another
5mW to 10mW for the opamps in the loopfilter). Power consumption goes
down a bit with decreasing sample rate, but not as much as one would
hope for.

				Attila Kinali

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