[time-nuts] Odd-order multiplication of CMOS-output OCXO

Attila Kinali attila at kinali.ch
Tue Jan 21 00:15:45 UTC 2020


On Mon, 20 Jan 2020 15:40:08 -0800
Mark Haun <mark at hau.nz> wrote:

> I was about to say that adding a second ADC channel is really expensive
> (like $50 between AD9266 and AD9269), but I really like this idea...
> just couple a reference oscillator into the main signal path at an
> appropriate level, then use a parallel receive path in the FPGA
> to trim the NCOs for the known beacon frequency.

You don't need a high performance ADC for the reference as you are dealing
with a narrow band signal of known frequency. Even a 10bit or 8bit ADC
would be good enough. You can even go and sample at half frequency
and save both money and power. This works because the required bandwidth
of the signal to track properly is low, somewhere in the order of 1-10kHz
should be enough. Thus working with just a few bits on the ADC and then
decimating you get lots of bits. E.g. going from 40MHz to 40kHz results
in approximately 9bits more. Starting from a 8bit ADC this gives something
around 15bits (probably more like 12-14bits, not accounting for ADC and
sampling noise and numerical precision), which is already good enough
to track at a rate of 100-500Hz.

If you choose a different frequency for the sampling clock, that is
"odd", let's say 155.52MHz/2=77.76MHz, you can sample even further
down (e.g. at 7.776MHz) and get to lower cost and lower power ADCs.

There is one key parameter for this ADC that you should not skimp on, though.
It's apperture jitter, as this directly translates into tracking noise of
the reference.


> Unfortunately I suspect the added digital power consumption in the FPGA
> would be greater than the analog power for a PLL solution.  As much as
> it pains me to say that as a DSP guy ;)  I need to think about this
> some more, though.

Hmm... My gut feeling would say that the ADC+tracking approach should
be lower power... But I have not done the calculation, so I might be wrong.
But yes, there are several design choices and trade-offs that need to be
balanced, that directly affect cost and power consumption.

				Attila Kinali
-- 
<JaberWorky>	The bad part of Zurich is where the degenerates
                throw DARK chocolate at you.




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