[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mark Haun]

On Mon, 20 Jan 2020 17:31:51 -0500
Bob kb8tq <kb8tq at n1k.org> wrote:
> > On Jan 20, 2020, at 5:16 PM, jimlux <jimlux at earthlink.net> wrote:
> > On 1/20/20 1:57 PM, Attila Kinali wrote:
> >> And then there ia third way, which is IMHO even better:
> >> Your application is an SDR system, i.e. you already need some
> >> signal processing for the system to work. Why not extend this
> >> to use it for the reference as well? Add another ADC and feed
> >> the reference signal to that, then track the phase/frequency
> >> relation between the sampling clock and the reference and
> >> compensate any drift in the signal path. This way you get to
> >> disable the reference if it is not needed and save a lot of power
> >> and at the same time are able to use references with any frequency
> >> and can change the "loop frequency" freely without the need to
> >> worry about PLL stability or tempco of filters in the multiplier
> >> version.  
> > 
> > This ...
> > 
> > This is the way of the future.  The problem is that there are
> > enough legacy systems out there where you need "control" vs
> > "knowledge"
> > 
> > And, in the SDR world: while theoretically, you can do this in
> > software, a lot of times the software is either a black box, or
> > incomprehensible in finite time, or architected in a way that makes
> > it hard, that it's actually faster and easier to discipline the
> > reference oscillator than to fix the software.  
> 
> If your “reference” is a 10 MHz OCXO, that may well come down on top
> / very near something you might want to receive. Having seen what WWV
> uses as an exciter … indeed their noise “as transmitted” is pretty
> darn good. 
> 
> If the reference is 16.384 …. hmmm …. maybe not so much. I can’t
> think of much around there worth tuning in to. Simply feeding the
> OCXO (at a very low level) into a single ADC might well do the trick.
> ( yes, you have a number of things to dig into, it’s not quite the
> slam dunk I’m making it out to be).

I was about to say that adding a second ADC channel is really expensive
(like $50 between AD9266 and AD9269), but I really like this idea...
just couple a reference oscillator into the main signal path at an
appropriate level, then use a parallel receive path in the FPGA
to trim the NCOs for the known beacon frequency.

Unfortunately I suspect the added digital power consumption in the FPGA
would be greater than the analog power for a PLL solution.  As much as
it pains me to say that as a DSP guy ;)  I need to think about this
some more, though.

Thanks for the ideas,
Mark