[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Mike Ingle]

Hi All,

I am not an expert here, but I can say with some certainty that a divided
clock works well.  I have a system with a 4GSPS RF ADC and a aux ADC which
runs at 1/64th the RF ADC.  The whole clock chain is a 10MHz ext ref -> a
LMX2581 synth -> RF ADC -> RF ADC DCO -> nb4l52 clk in with a D coming from
an FPGA as the AUX ADC clock.  The AUX ADC is able to time stamp a 1pps to
a 1sigma of less than 15ps (difference between the 1PPS into the AUX ADC
and a copy into the RF channel).

The point being what is wrong with a good 80MHz ocxo or tcxo for the main
ADC and and a divided by 4 or 5 to an aux ADC?  And, I have made an HF
transceiver with a ltc2195 and a simple 125MHz ECL oscillator, and some
250MSPS Analog devices DAC which managed QAM256.

It seems like this is being a little over thought.

Run your main ADC at 80MSPS, and free run your oscillator, and present a
reference either through a aux ADC, or as a secondary clock to an FPGA.  No
need to multiply.

-- mike





On Tue, Jan 21, 2020 at 8:25 PM jimlux <jimlux at earthlink.net> wrote:

> On 1/21/20 10:41 AM, Mark Haun wrote:
> > Hi Attila,
> >
> > On Tue, 21 Jan 2020 15:08:16 +0100
> > Attila Kinali <attila at kinali.ch> wrote:
> >> On Tue, 21 Jan 2020 01:15:45 +0100
> >> Attila Kinali <attila at kinali.ch> wrote:
> >>> You don't need a high performance ADC for the reference as you are
> >>> dealing with a narrow band signal of known frequency. Even a 10bit
> >>> or 8bit ADC would be good enough. You can even go and sample at
> >>> half frequency and save both money and power.
> >>
> >> I just spend a few minutes looking at ADCs and found the LTC2256-12
> >> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
> >> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
> >> respectively. 3dB BW is 800MHz, so more then good enough to even use
> >> the 100MHz output of an hydrogen maser, if you want a really good
> >> reference ;-)
> >>
> >> Power consumption at max sample rate are 34mW and 47mW respectively.
> >> That's slightly more than a PLL would use (~20mW, plus maybe another
> >> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
> >> down a bit with decreasing sample rate, but not as much as one would
> >> hope for.
> >
> > I hope you will indulge one more newbie question on the analog PLL
> > option... as I have approximately zero experience designing them.
> >
> > What are the adverse consequences of using large divisors in the loop,
> > as would be required for my odd OCXO frequency?  E.g. on paper, it would
> > seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
> > frequency.  How would this differ from a more "normal" ref clock
> > frequency of 10 or 16 MHz with smaller divisors?
> >
>
>
> You have potential spurs at the PFD frequency and multiples of it, so it
> kind of depends on what bandwidths you have in things like the loop
> filter and downstream in the output path.  A higher comparison frequency
> puts the first spur farther out.
>
>
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