[time-nuts] New Subscriber, DIY GPSDO project (yes, another one)

[Tobias Pluess]

Hi,
I am sure it is theoretically possible to find an optimal control loop
design if you have accurate models of the OCXO and for the behaviour of the
1PPS pulse.
TvB has written a GPSDO simulator which allows to code different PLL and
control algorithms. I have implemented something similar in Matlab.
Basically, if you know the VCO tuning characteristics and the phase
detector constant, then you can use procedures as described in the PLL
books that are out there (I have ond from R. Best).

But I agree that it is perhaps a very difficult problem -  you cannot
simply try out different algorithms because each time it takes days to wait
until everything has settled and stabilised, then you need to record that
data etc.

Maybe the easiest way is indeed using the GPSDO simulator.
If there is some interest, I could perhaps post my Matlab code. It plots
nicely the calculated EFC voltage and simumates the OCXOs frequency
variation as the EFC is varied.

Best
Tobias
HB9FSX


On Sat., 7 Mar. 2020, 12:36 Gilles Clement, <clemgill at gmail.com> wrote:

> Hi,
> How do you optimally tune the control loop time constant ?
> (Mine gets quite unstable when the update rate is slow - and the amplitude
> of the change step low - enough not to degrade the OCXO performance )
> Is there a method described somewhere (like the Ziegler–Nichols method for
> PID) ?
> Thx,
> Gilles.
>
> > Le 3 mars 2020 à 18:28, Attila Kinali <attila at kinali.ch> a écrit :
> >
> > On Tue, 3 Mar 2020 12:14:37 -0500
> > Jim Harman <j99harman at gmail.com> wrote:
> >
> >> I don't understand why you say the DAC should have a resolution of 24-30
> >> bits. I can see that the loop time constant affects the precision
> needed in
> >> the filter calculations, but what does the time constant have to do with
> >> the needed DAC resolution? We don't have to wait for the whole time
> >> constant before changing the DAC, we can update the filter calculations
> and
> >> look at its output every second and adjust the DAC whenever the PI
> filtered
> >> phase error is one DAC step or more.
> >
> > You do wait the whole time before updating the DAC value.. kind of ish.
> > The control loop's time constant is exactly that: The time it takes
> > the control loop for a change in the input to affect the output (very
> > loosely speaking). Yes, the sample rate at which the loop runs is
> > much higher, but that doesn't change the fact that the loop is slow
> > to react. And you want it to be slow to react, as otherwise the high
> > noise of GPS degrades the performance of your OCXO.
> >
> >> If the OCXO has a tuning range of 1 ppm and we want frequency control
> >> of 1e-12, wouldn't that require a DAC with 1e6 steps or 20 bits,
> >> assuming the DAC covers the full tuning range of the oscillator?
> >
> > Yes. There is a calculation mistake in there. I corrected it in
> > the next mail:
> >
> http://lists.febo.com/pipermail/time-nuts_lists.febo.com/2019-October/097963.html
> >
> >                       Attila Kinali
> >
> > --
> > <JaberWorky>  The bad part of Zurich is where the degenerates
> >                throw DARK chocolate at you.
> >
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