[time-nuts] Noise Floor

[John Miles]

> And then, getting the data reliably out of the ADC into the FPGA, and
> synchronized across multiple channels. That particular part doesn't
> guarantee the startup state of the internal pipeline.

There's a sync pin for use with the clock divider, but AFAIK it does nothing
when the divider isn't used (which it isn't).  Fortunately, fixed delay
between channels isn't a big concern, as long as it stays put.  With a 1:1
clock, the time from clock in to DCO out is always consistent.  

> is that because of connectors and interfaces?
> Or because of "unit test" time and process?

Mostly the former, as we test the system as a whole.  Multiple boards cost
more at the PCB fab and cost more to stuff, and of course the interconnects
are both an expense on the BOM and a liability during assembly. The front
panel and input PCB alone have two dozen SMA jacks, so assembly training and
documentation isn't a trivial matter.

Then there's the additional mounting hardware and assembly steps associated
with multiple boards.  And while we test at the system level as noted, the
test script has to do its best to narrow down failures at the subassembly
level, rather than simply reporting go/no-go conditions.  Lots of little
things that add up to real costs. 
 
> I know that for space stuff, all on one board or in one box is cheaper
> than breaking it up, particularly for RF systems. Because if it's
> individual widgets, everyone wants individual test data at the widget
> level, before you combine them into superwidget assemblies.

Yes, and I'm sure the cost of the interconnects and mounting hardware is
insane in that business!

-- john