[time-nuts] Noise Floor

[Bob kb8tq]

Hi

> On Mar 24, 2020, at 7:31 PM, jimlux <jimlux at earthlink.net> wrote:
> 
> On 3/24/20 2:17 PM, John Miles wrote:
>>>> It would be interesting to know what ADC was used and if there's an
>>>> SDR-board out there that uses the same ADC.
>>> 
>>> Uh.. I remember John telling me what ADC it was, but I forgot, sorry.
>> It uses four AD9265s.  The TimePod used four LTC2216s, but the AD9265s
>> support higher clock rates with less power consumption, and both of those
>> attributes were important this time around.
> 
> And they work in space, should one care about that.. They also have nice low clock input noise.
> (i.e. the SNR isn't too degraded from the ideal, compared to some other fast ADCs).
> 
> 
>>> I am pretty sure I could design something like the PhaseStation as well.
>>> The working principle is easy and can be explained on a napkin in 5
>> minutes.
>>> But getting it to this remarkable perfomrance? Not without a lot of
>>> trial and error. And even then, I wouldn't be sure.
>> I don't think there's any way to avoid the trial-and-error part unless you
>> have the luxury of an unlimited ceiling for both the R&D budget and the
>> target retail price, and maybe not even then.  One reason it took longer
>> than expected to ship the 53100A was that a lot of lessons that I *thought*
>> had been adequately learned on the 5330A/3120A project didn't pay off when
>> different ADCs were used, and when the carrier and offset frequency
>> requirements grew by 6x and 10x respectively.
>> With the TimePod, for example, noise and spur performance weren't strongly
>> influenced by ADC clock distribution.  On PhaseStation, that particular
>> "unlearned lesson" cost me a respin.
> 
> That is a real lesson - It's one that people doing their first low noise systems get burned by (do NOT run your clock signal from your quiet oscillator through the FPGA, and yes, that fancy fast clock driver might actually degrade performance because it has a 1GHz BW and so does the clock input on the ADC...)
> 
> And then, getting the data reliably out of the ADC into the FPGA, and synchronized across multiple channels. That particular part doesn't guarantee the startup state of the internal pipeline.
> 
> 
> 
>> Keeping parts and manufacturing costs under control was also more difficult
>> than anticipated.  Another lesson that wasn't learned soon enough was that a
>> design with four or five internal PCBs ends up being much more expensive
>> than one that uses only two, even if the total board area is similar.  We
>> had to increase the price twice to maintain standard T&M industry margins,
>> and (having just come back from visiting Said and Giovanni at Jackson Labs)
>> that's about to happen again.  The original vision of a four-figure price
>> tag was unrealistic, and that's definitely a lesson for next time.
> 
> is that because of connectors and interfaces?
> Or because of "unit test" time and process?
> 
> I know that for space stuff, all on one board or in one box is cheaper than breaking it up, particularly for RF systems. Because if it's individual widgets, everyone wants individual test data at the widget level, before you combine them into superwidget assemblies.


If you are building an oscillator, you run into the same thing. Part of the issue
is simply that each board has some sort of testing / minimum charge. Split 
the board into quarters and the price goes up significantly. As soon as you 
set it up for assembly, you hit the same sort of cost issues. It then goes into
some sort of test process … cost goes up yet again ….

Bob

> 
> 
> 
>> -- john, KE5FX
>> Miles Design LLC / Jackson Labs Technologies, Inc.
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> 
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