[time-nuts] Question for my new GPSDO

[Attila Kinali]

Hoi Tobias,

On Mon, 7 Oct 2019 21:06:37 +0000
Tobias Pluess <tobias.pluess at xwmail.ch> wrote:

> I am planning to make a new version of my own GPSDO. I have attached the 
> schematic of the OCXO and DAC. Because the stability of my previous design 
> was not yet optimal, I now chose better components; my main criteria was the 
> lowest tempco I found.
> As one can see, I plan to use the DAC8560, which is a 16-bit DAC having an 
> internal 2ppm/K voltage reference. Alternatively, the DAC8501 could be used, 
> which requires an external voltage reference for which I selected the ADR441B 
> (typically 1ppm/K).

I think, you are optimizing for the wrong thing. 
While temperature coefficient is important, it is not as important as you
think. Unless you want to operate your GPSDO outside or where you expect
large temperature swings. Instead, what you do is give your whole GPSDO
enough thermal mass, such that you don't see a significant temperature
change at time scales shorter than the loop time constant. Worst case,
I'd rather heat up the PCB using some simple resistive heater (ie have
a thin meander line on one layer, coupled with an NTC thermistor and some
cheap, opamp based PI control loop)

What, I think, you haven't had a look at is the resolution of your DAC.
You get, including your resistive divider a 17bit resolution. But this
is not enough. You want to be able to control the OCXO such, that at
the loop time constant, you have less than 1LSB offset in frequency.
Usualy people aim for something in the order of 1000s as loop time constant,
often even longer than that. Assuming your GPS receiver gives you approximately
1ns RMS jitter (probably worse than that, but it makes it easy to calculate)
that would mean frequency control of the level of 1e-12 is required. Assuming
your OCXO has a tuning range of 1ppm (I've seen 0.1 to 20ppm for OCXOs)
that would mean you have to controll the EFC voltage better than parts in 1e-9
or 30 bits. Yes, this is kind of unreallistic, but that's what the design
should aim for. If you acheive something around 24bits, you will be probably
close enough. (Note: that's 24bit resolution and stability over the
loop time constant. It is not 24bit absolute resolution)

Attached is my take on how to do this, from an old attempt on designing
a GPSDO. As reference an LTC6655 is used (mostly for its low noise, not
for its high stability). An LTZ1000 would be better, but also much more
expensive. The AD5060 acts as a (reasonably) low noise DAC with 16bit.
The DAC is supposed to be dithered using software control and the ADG633
is meant to 1) supress the DAC's glitch (both digital-to-analog and code)
and 2) provide stable timing of when the DAC output is applied. The whole
thing is followed by a filter. The structure is kind of weird, but made
such to give selectable range: 0-5V, 0-10V, -5-+5V, -10-+10V. The LTC2057
is probably overkill in this application. But it's reasonably cheap 
and rail-to-rail input and output, which simplifies the design quite 
considerably.

One thing I would differently, though, would be to replace the DAC and
the CMOS switch by an AD5542. The glitch of the DAC is usally in the order
of what can be acheived with an CMOS switch, so there is little to be
gained there. The digital-to-analog glitches should be high enough in
frequency that they probably shouldn't cause much degradation after
passing through the low-pass filter. The load pin of the AD5542 would
serve to give appropriate timing precision for the dithering to work.
It also has much lower low frequency noise. With the DAC replaced and
the CMOS switch gone, this design should, at least on paper, lead to
approximately 24bits of noise free bits.

As a design guideline to select DACs for this kind of application:
Ignore INL, it will not matter as the control loop will take care 
of that. DNL _must_ be below 1LSB as otherwise the control loop
has to deal with sudenly inverted loop gain. the lower DNL, the better
for applications where you dither. The DAC output should be as low
noise as possible, as this noise will dominate all other noise (safe
for the reference noise). And the important noise is the low frequency
noise, not the white noise density. Only after these comes temperature
coefficients (offset and gain).

And the dithering algorithm to use should be a delta-sigma modulator.
At least a second order, better a 3rd or 4th order to keep idle tones
low. Or use additional dithering techniques to reduce idle tones.
There are also techniques to reduce effects due to DNL but going into that
would make this mail even longer than it already is. So I just point
at the delta-sigma modulator book: "Understanding Delta Sigma Data
Converters" by Schreier, Pavan and Temes.

BTW: If anyone has an idea how to get more noise free bits for this
kind of application, I would very much like to hear them. I've been
thinking about this for quite some time, but cannot come up with a
better solution.


			Attila Kinali

-- 
It is upon moral qualities that a society is ultimately founded. All 
the prosperity and technological sophistication in the world is of no 
use without that foundation.
                 -- Miss Matheson, The Diamond Age, Neal Stephenson
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