[time-nuts] Frequency division by 81

[Mike Ingle]

Hi Gilles,  I didn't peruse the linked paper, but I usually use a re-sync
FF MC100ep51 or 52  with the clock at the pre-divider rate, and the "D"
coming from in my case an FPGA.  thai eliminates the phase noise
contributed by the FPGA.  The nice thing with an FPGA, is you can use the
LVDS outputs into the differential ECL D pretty easily.  And  ECL is
clean.  --mike

On Thu, Jun 18, 2020 at 5:42 PM Gilles Clement <clemgill at gmail.com> wrote:

> Hi
> I need to divide the output of an OCXO by a factor D=81 for testing
> purposes. So with minimum added phase noise.
> PICDIV-like approches would not work (D needs to be divisible by 8 or at
> least be even)
> I went through the archives and it seems that an Injection Locked
> Frequency Divider with resynchronization flip-flop could be a simple and
> acceptable solution.
> As described in the following Wenzel paper: Unusual Frequency
> Dividerswww.wenzel.com › uploads › dividers <
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwik49qGpIvqAhURahQKHTBVClAQFjABegQIARAB&url=http%3A%2F%2Fwww.wenzel.com%2Fwp-content%2Fuploads%2Fdividers.pdf&usg=AOvVaw2m-9lURROiSbG9XykiDNDU
> >
> Does this make sense?
> Gilles.
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