[time-nuts] Frequency division by 81

[Gerhard Hoffmann]

Am 19.06.20 um 11:42 schrieb Clint Jay:
> 12F675 is specified for clock input of 20MHz and (without digging too 
> deep into the way the code works) I think the PICDiv code works with 
> clock input rather than input to a timer or counter peripheral so 
> 20MHz would be fine. While I'd not recommend it for use I have seen 
> them run (experimentally) at 27MHz and I've seen anecdotal reports of 
> over 30MHz. 
Burn the attachment into something like this:

< 
https://www.ebay.de/itm/Coolrunner-rev-C-fur-Jasper-Trinity-Corona-Phat-Slim-Kabelpuls-IC-Xbox-36-tp/353110312086?_trkparms=aid%3D1110006%26algo%3DHOMESPLICE.SIM%26ao%3D1%26asc%3D20200520130048%26meid%3D477f5b9f172e4c9b92d885140d5a8df0%26pid%3D100005%26rk%3D1%26rkt%3D2%26mehot%3Dco%26sd%3D402298757019%26itm%3D353110312086%26pmt%3D1%26noa%3D0%26pg%3D2047675%26algv%3DSimplAMLv5PairwiseWebWithBBEV2bDemotion%26brand%3DMarkenlos&_trksid=p2047675.c100005.m1851 
                          >

and you're done.

Add sine/square converter in front if neededand output precision 
flipflop if standard CMOS is not good enough.

I have my own stamp-sized Coolrunner II board, never tested this one. 
One could also program a phase comparator and/or 1pps generation from 
100 MHz into it. BTDT. I might provide the Gerbers for JLCPCB.

regards, Gerhard

---------------------------------------------

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;
use     ieee.numeric_std.all;

entity div81 is
     Port(
         clk:  in   std_logic;   -- CMOS clock to > 200 MHz in
         q:    out  std_logic    -- divided output
     )
end div81;

architecture beehive of div81 is

     signal tctr:  integer range 0 to 80;

     attribute LOC: string;
     attribute IOSTANDARD: string;
     attribute LOC of clk:         signal is "P1";  -- in put is pad 1
     attribute IOSTANDARD of clk:  signal is "LVCMOS33";
     attribute LOC of q:           signal is "p31"; -- output is pad 31
     attribute IOSTANDARD of q:    signal is "LVCMOS33";

     -- (function boolean_to_standard_logic no more needed in more 
modern VHDL)
     function bool2sl(b : boolean) return std_logic is
     begin
         if b then
             return '1';
         else
             return '0';
         end if;
     end function bool2sl;

begin

u_div : process(clk) is   -- this block wakes up if something happens on 
clock pin
     begin
         if rising_edge(clk) then

             if (tctr = 80)
             then
                 tctr <= 0;          -- reset if maximum count reached
             else
                 tctr <= tctr + 1;   -- else just increment
             end if;

             q <= bool2sl(tctr < 40); -- set output high/low time to taste
         end if;   -- rising_edge()
     end process u_div;

end beehive;