[time-nuts] Re: Lowest noise (phase noise and ADEV) method to achieve 10 MHz signal from 5 MHz input
Mike Feher
mfeher at eozinc.com
Mon Nov 29 12:01:36 UTC 2021
I see you are using two for the phase noise test setup (a common way of
doing it). I am curious about the phase matching between units. From the
results it appears they must be pretty well matched, but did not see any
actual data. Since it is over a very narrow frequency BW it should be no
problem. Thanks & Regards - Mike
Mike B. Feher, N4FS
89 Arnold Blvd.
Howell NJ 07731
848-245-9115
-----Original Message-----
From: timeok at timeok.it <timeok at timeok.it>
Sent: Monday, November 29, 2021 4:35 AM
To: time-nuts at lists.febo.com
Subject: [time-nuts] Re: Lowest noise (phase noise and ADEV) method to
achieve 10 MHz signal from 5 MHz input
you can use this:
http://www.timeok.it/wp-content/uploads/2015/08/high-performance-frequency-d
oublerv1-31.pdf
Luciano P. S. Paramithiotti
timeok at timeok.it
www.timeok.it
Da "Matt Huszagh" huszaghmatt at gmail.com
A time-nuts at lists.febo.com
Cc
Data Sun, 28 Nov 2021 19:29:58 -0800
Oggetto [time-nuts] Lowest noise (phase noise and ADEV) method to achieve
10 MHz signal from 5 MHz input
Hi,
I've got a 10 MHz distribution amplifier and am considering purchasing a
5 MHz reference. Most (not all) of my equipment accepts a 5 MHz
reference, but I'd like to be able to use the existing distribution
amplifier I have if possible. Therefore, I'm considering ways I might
generate a low-noise 10 MHz signal from the 5 MHz reference.
An obvious way is to use a doubler. However, as I understand it, even an
ideal doubler will add 20log(2)=6 dB of phase noise to the 10 MHz
signal. It seems like a possibly more expensive, but lower noise way
would be to use a PLL with a divider that locks the divided 10 MHz
signal to the 5 MHz input. If the time constant of the loop filter is
set long enough, does this avoid the phase noise multiplication issue?
From what I've gathered, this is a technique HP used in some of their
gear. For example, the 8566 and 8340/1 lock a 100 MHz VCXO to an
external reference with a PLL.
Any other thoughts on this?
Matt
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