[time-nuts] Re: Lowest noise (phase noise and ADEV) method to achieve 10 MHz signal from 5 MHz input

[Bob kb8tq]

Hi

The PLL will have the same 20 log N issue plus a number of other 
problems. The big question is: what are you after? 

If you need something below -175 dbc / Hz far removed, what is 
the application? There may well be better ways to do this or that. 

If you are after -125 dbc / Hz at 1 Hz, that’s a very different need and
the approach to getting it would be significantly different. 

Simple answer is that most equipment is not all that sensitive to phase
noise and that distribution amps have a noise floor. You can go nuts
getting a super quiet reference and it will have no real impact outside
a few very specific applications. ( which likely will need custom “plumbing”).

Bob

> On Nov 28, 2021, at 10:29 PM, Matt Huszagh <huszaghmatt at gmail.com> wrote:
> 
> Hi,
> 
> I've got a 10 MHz distribution amplifier and am considering purchasing a
> 5 MHz reference. Most (not all) of my equipment accepts a 5 MHz
> reference, but I'd like to be able to use the existing distribution
> amplifier I have if possible. Therefore, I'm considering ways I might
> generate a low-noise 10 MHz signal from the 5 MHz reference.
> 
> An obvious way is to use a doubler. However, as I understand it, even an
> ideal doubler will add 20log(2)=6 dB of phase noise to the 10 MHz
> signal. It seems like a possibly more expensive, but lower noise way
> would be to use a PLL with a divider that locks the divided 10 MHz
> signal to the 5 MHz input. If the time constant of the loop filter is
> set long enough, does this avoid the phase noise multiplication issue?
> From what I've gathered, this is a technique HP used in some of their
> gear. For example, the 8566 and 8340/1 lock a 100 MHz VCXO to an
> external reference with a PLL.
> 
> Any other thoughts on this?
> Matt
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