[time-nuts] Working on a low-phase-noise frequency multiplier

[Bill Ezell]

I have some old frequency standards that provide 1, 2.5, or 5 Mhz 
outputs, not great for comparing against modern 10Mhz standards.

I could do a divider, pretty easy, but only useful for doing analysis. 
Better to have 10Mhz output.

So, I'm thinking a multiplier. There are many versions, from simple 
diode ones and up.

It seems that doing an integer-N PLL with a VCXO would be the way to go. 
The capture range can be quite narrow since the input will be something 
that's within a 1 Hz range and a long loop constant might be good. Plus, 
with a good-quality VCXO, I would expect the noise figure to match the 
VCXO's pretty closely.

Any comments before I wander off into la-la land? BTW, Analog Devices 
has some good PLL design tools.

So, what sparked this? I bought one of the Sulters that was mentioned a 
while back, 2.5Mcycles (gotta be historically accurate). I also have an 
equally-ancient Vectron double-oven std that, last I tested it, was down 
in the e-11 or better range. I also got a TinyVNA which is now a 
TinyPFA, and it can only deal with equal freq inputs. I want to also 
compare that against my HP 5370 and 53310. You can see the slippery slope.

Thanks, Bill

-- 
Bill Ezell
I happen to know that this is the Lupin Express.