[time-nuts] Odd-order multiplication of CMOS-output OCXO

jimlux jimlux at earthlink.net
Wed Jan 22 00:11:43 UTC 2020


On 1/21/20 3:30 PM, Magnus Danielson wrote:
> Hi Mark,
> 
> On 2020-01-21 19:41, Mark Haun wrote:
>> Hi Attila,
>>
>> On Tue, 21 Jan 2020 15:08:16 +0100
>> Attila Kinali <attila at kinali.ch> wrote:
>>> On Tue, 21 Jan 2020 01:15:45 +0100
>>> Attila Kinali <attila at kinali.ch> wrote:
>>>> You don't need a high performance ADC for the reference as you are
>>>> dealing with a narrow band signal of known frequency. Even a 10bit
>>>> or 8bit ADC would be good enough. You can even go and sample at
>>>> half frequency and save both money and power.
>>> I just spend a few minutes looking at ADCs and found the LTC2256-12
>>> and its faster sister LTC2257-12. They go for ~15USD at quantity 1.
>>> Both have 170fs RMS apperture jitter and do 25Msps and 40Msps
>>> respectively. 3dB BW is 800MHz, so more then good enough to even use
>>> the 100MHz output of an hydrogen maser, if you want a really good
>>> reference ;-)
>>>
>>> Power consumption at max sample rate are 34mW and 47mW respectively.
>>> That's slightly more than a PLL would use (~20mW, plus maybe another
>>> 5mW to 10mW for the opamps in the loopfilter). Power consumption goes
>>> down a bit with decreasing sample rate, but not as much as one would
>>> hope for.
>> I hope you will indulge one more newbie question on the analog PLL
>> option... as I have approximately zero experience designing them.
>>
>> What are the adverse consequences of using large divisors in the loop,
>> as would be required for my odd OCXO frequency?  E.g. on paper, it would
>> seem that I could use 80 MHz / 625 = 16.384 MHz / 128 = 128 kHz PFD
>> frequency.  How would this differ from a more "normal" ref clock
>> frequency of 10 or 16 MHz with smaller divisors?
> 
>  From my experience, such factors and rate of phase comparator is
> relatively easy to work with and get to work reasonably well for most
> purposes. I recommend you to use a PI-loop.
> 
> For a step-up you want to keep the PLL bandwidth fairly large, and that
> helps making it easy.
> 
> I've been tempted to do a bunch of such loops in various kinds of
> equipment to solve issues. I should to more of them. One should have a
> nice little lock-up board to just apply.
> 

One might also look at a fractional-N PLL - just a bit more flexibility 
in where the spurs go.





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