[time-nuts] Odd-order multiplication of CMOS-output OCXO

[Bob kb8tq]

Hi

> On Jan 21, 2020, at 8:21 PM, Magnus Danielson <magnus at rubidium.se> wrote:
> 
> Hi,
> 
> On 2020-01-22 01:05, Mark Haun wrote:
>> On Wed, 22 Jan 2020 00:30:12 +0100
>> Magnus Danielson <magnus at rubidium.se> wrote:
>>>> What are the adverse consequences of using large divisors in the
>>>> loop, as would be required for my odd OCXO frequency?  E.g. on
>>>> paper, it would seem that I could use 80 MHz / 625 = 16.384 MHz /
>>>> 128 = 128 kHz PFD frequency.  How would this differ from a more
>>>> "normal" ref clock frequency of 10 or 16 MHz with smaller divisors?
>>> From my experience, such factors and rate of phase comparator is
>>> relatively easy to work with and get to work reasonably well for most
>>> purposes. I recommend you to use a PI-loop.
>>> 
>>> For a step-up you want to keep the PLL bandwidth fairly large, and
>>> that helps making it easy.
>> Why is this?  In my primitive understanding, the loop bandwidth sets the
>> point where the phase-noise characteristics of the reference and the
>> VCO are "glued together."  Because my VCXO has good phase noise, and
>> lacks only stability (say 0.1 to 1 sec and longer), I would have
>> thought I would want a small bandwidth---basically I want to preserve
>> the phase-noise characteristics but keep it from drifting.
> 
> With higher bandwidth, it follows the reference tighter. Consider that
> the bandwidth of the PLL is related to the time-constant for it to react
> to both the reference and the steered oscillator, and it will low-pass
> filter the reference and high-pass filter the steered oscillator, and
> higher bandwidth thus suppress more variations of the steered
> oscillator, relaxing thermal issues for instance.
> 
> If you have a loop filter being a low-pass filter rather than PI-loop,
> then you also get better lock-range, quicker lock-in and smaller
> phase-errors due to thermal effects or oscillator differences. For a
> PI-loop you essentially remove it from being an issue anyway and you can
> focus your bandwidth on phase-noise considerations, but the high-pass
> vs. low-pass balance remains an issue for compromise.
> 
> For step-up PLLs, you typically wants a high bandwidth to keep tight
> phase with the reference, but for a clean-up PLL you want a low
> bandwidth to filter out as much noise from the reference.
> 
> As you compare the phase-noise of the reference and steered oscillator,
> as compared on the same frequency, the optimum bandwidth is usually
> where they cross each other. This assumes that you actually considered
> all the variations.


…….. and *assuming* the noise floor of the dividers and the noise floor of the phase
detector is anywhere near good enough to be useful compared to your super duper
low noise oscillators ….. With good OCXO’s and VCXO’s this may indeed be a gotcha. 
With a simple VCO and TCXO from “low bidder industries” , maybe not so much. 

( in genera with good oscillators l, this forces you to a narrower loop than you might 
have anticipated ….) 

Again, playing with simulation software  just might be a good idea. For the brave, you
can buy various books and dig up all sorts of formulas. Those can be dumped into 
spread sheets and validated ….. 

Bob


> 
> Cheers,
> Magnus
> 
> 
> 
> 
> _______________________________________________
> time-nuts mailing list -- time-nuts at lists.febo.com
> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
> and follow the instructions there.