[time-nuts] Re: What phase variations to expect in a DMTD due to temperature fluctuations?

[Carsten Andrich]

Hi Erik,

only the ADC clock should matter and the used ADC should be of the 
simultaneous sampling type. If it's not, its multiplexer may have a 
detrimental temperature-dependent effect on the phase measurement.

I've implemented a fully digital DMTD using USRP N210 with LFRX 
daughterboards [1]. To analyze stability of the system itself, I 
compared a split 10 MHz signal. Over the course of 4 days, the measured 
standard deviation was 359 fs [1, Fig. 11]. I don't have temperature 
measurements available, but the lab wasn't air conditioned, populated, 
and diurnal difference between two SRS FS725 was clearly observable 
(another measurement not in the paper).

The high stability could be explained by the N210's dual-channel ADC 
that directly sampled both 10 MHz signals. I believe, temperature 
differences between the preceding analog components (most importantly 
the LFRX daughterboard) probably have a very limited effect on account 
of the negligible relative bandwidth of the measured 10 MHz signals' 
true frequency (a few (dozen) mHz vs. 10 MHz). If the 10 MHz were 
down-mixed to a few Hz in the analog domain, the relative bandwidth 
would increase substantially. Of course, that's just an educated guess. 
I did not investigate temperature stability when I wrote the paper.

Best regards,
Carsten

[1] https://arxiv.org/pdf/1803.01438.pdf

On 24.10.22 07:19, jeanmichel.friedt--- via time-nuts wrote:
>> The down converted input signals are converted to digital using an ADC. The
>> rest is DSP. No digital circuit triggering timers. Can the clock of the MCU
>> still have an impact? For sure the clock of the ADC can have an impact.
> I realized when completing http://jmfriedt.free.fr/ifcs2021.pdf that the only
> clock that matters in Software Defined Radio is the ADC clock which timestamps
> each and every sample, from which subsequent digital processing can recover the
> acquisition time. The digital processing system can be asynchronous, buffered, pipelined
> but the latency between acquisition and processing will not matter in an open
> loop analysis of the radiofrequency data. In the cited work we mistakenly believed
> initially that the CPU clock had to be steered, before realizing it was only the clock
> referencing the ADC (and the FPGA) that mattered.
>
> Best, JM
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