[time-nuts] Re: What phase variations to expect in a DMTD due to temperature fluctuations?

[Lux, Jim]

On 10/23/22 10:19 PM, jeanmichel.friedt--- via time-nuts wrote:
>> The down converted input signals are converted to digital using an ADC. The
>> rest is DSP. No digital circuit triggering timers. Can the clock of the MCU
>> still have an impact? For sure the clock of the ADC can have an impact.
> I realized when completing http://jmfriedt.free.fr/ifcs2021.pdf that the only
> clock that matters in Software Defined Radio is the ADC clock which timestamps
> each and every sample, from which subsequent digital processing can recover the
> acquisition time. The digital processing system can be asynchronous, buffered, pipelined
> but the latency between acquisition and processing will not matter in an open
> loop analysis of the radiofrequency data. In the cited work we mistakenly believed
> initially that the CPU clock had to be steered, before realizing it was only the clock
> referencing the ADC (and the FPGA) that mattered.


One thing to watch out for, though, is at the transition from ADC clock 
to CPU clock domains, you will have some sort of synchronizer, and you 
have to watch out for either metastability or an "off by one" kind of thing.

Perhaps an exception is a classic double buffer in hardware, where ADC 
loads a dual port memory with its clock, then CPU unloads the buffer, 
while ADC fills the other.  But you still have the uncertainty in the 
dual port mechanism.